FAN9611MX【PDF 4/35 页】IC PFC CTLR DUAL BCM 16-SOIC

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Sheet目录38

1页 2页 3页 [4页]5页 6页 7页 8页

?2008 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FAN9611 " Rev. 1.1.7

Pin Configuration

Figure 5. Pin Layout (Top-View)

Pin Definitions

Pin #

Name

Description

ZCD1

Zero Current Detector for Phase 1 of the interleaved boost power stage.

ZCD2

Zero Current Detector for Phase 2 of the interleaved boost power stage.

5VB

5V Bias. Bypass pin for the internal supply, which powers all control circuitry on the IC.

MOT

Maximum On-Time adjust for the individual power stages.

AGND

Analog Ground. Reference potential for all setup signals.

Soft-Start Capacitor. Connected to the non-inverting input of the error amplifier.

COMP

Compensation Network connection to the output of the g

error amplifier

Feedback pin to sense the converters output voltage; inverting input of the error amplifier.

OVP

Output Voltage monitor for the independent, second-level, latched OVP protection.

VIN

Input Voltage monitor for brownout protection and input-voltage feedforward.

PGND

Power Ground connection.

DRV2

Gate Drive Output for Phase 2 of the interleaved boost power stage.

DRV1

Gate Drive Output for Phase 1 of the interleaved boost power stage.

VDD

External Bias Supply for the IC.

CS2

Current Sense Input for Phase 2 of the interleaved boost power stage.

CS1

Current Sense Input for Phase 1 of the interleaved boost power stage.

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